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(R)
HS-303ARH, HS-303BRH
Data Sheet July 7, 2008 FN6411.1
Radiation Hardened CMOS Dual SPDT Analog Switch
The HS-303ARH and HS-303BRH analog switches are monolithic devices fabricated using Intersil's dielectrically isolated Radiation Hardened Silicon Gate (RSG) process technology to insure latch-up free operation. They are pinout compatible and functionally equivalent to the HS-303RH, but offer improved 300kRAD(Si) total dose capability. These switches offers low-resistance switching performance for analog voltages up to the supply rails. "ON" resistance is low and stays reasonably constant over the full range of operating voltage and current. "ON" resistance also stays reasonably constant when exposed to radiation. Break-before-make switching is controlled by 5V digital inputs. The HS-303ARH should be operated with nominal 15V supplies, while the HS-303BRH should be operated with nominal 12V supplies.
Features
* QML, Per MIL-PRF-38535 * Radiation Performance - Total Dose: 3x105 RAD(Si) - SEE: For LET = 60MeV-mg/cm2 at 60 Incident Angle, <150pC Charge Transferred to the Output of an Off Switch * No Latch-Up, Dielectrically Isolated Device Islands * Pinout and Functionally Compatible with Intersil HS-303RH and HI-303 Series Analog Switches * Analog Signal Range Equal to the Supply Voltage Range * Low Leakage . . . . . . . . . . . . . . . . 100nA (Max, Post-Rad) * Low rON . . . . . . . . . . . . . . . . . . . . . . 70 (Max, Post-Rad) * Low Standby Supply Current . . . . . . . . . . +150A/-100A (Max, Post-Rad)
Specifications
Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the HS-303ARH and HS-303BRH are contained in SMD 5962-95813. A "hot-link" is provided from our website for downloading
Pinouts
HS1-303ARH, HS-303BRH (SBDIP), CDIP2-T14 TOP VIEW
NC S3 D3 D1 S1 IN1 GND 1 2 3 4 5 6 7 14 V+ 13 S4 12 D4 11 D2 10 S2 9 IN2 8 V-
HS9-303ARH, HS-303BRH (FLATPACK) CDFP3-F14 TOP VIEW
1 NC S3 D3 D1 S1 IN1 GND 2 3 4 5 6 7 14 13 12 11 10 9 8 V+ S4 D4 D2 S2 IN2 V-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HS-303ARH, HS-303BRH Ordering Information
ORDERING NUMBER 5962F9581304QCC 5962F9581304QXC 5962F9581304V9A 5962F9581304VCC 5962F9581304VXC HS0-303ARH/SAMPLE HS1-303ARH/PROTO HS9-303ARH/PROTO 5962F9581305QCC 5962F9581305QXC 5962F9581305V9A 5962F9581305VCC 5962F9581305VXC HS0-303BRH/SAMPLE HS1-303BRH/PROTO HS9-303BRH/PROTO PART NUMBER HS1-303ARH-8 HS9-303ARH-8 HS0-303ARH-Q HS1-303ARH-Q HS9-303ARH-Q HS0-303ARH/SAMPLE HS1-303ARH/PROTO HS9-303ARH/PROTO HS1-303BRH-8 HS9-303BRH-8 HS0-303BRH-Q HS1-303BRH-Q HS9-303BRH-Q HS0-303BRH/SAMPLE HS1-303BRH/PROTO HS9-303BRH/PROTO TEMP. RANGE (C) -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 14 LD SBDIP 14 LD Flatpack D14.3 K14.A 14 LD SBDIP 14 LD Flatpack 14 LD SBDIP 14 LD Flatpack 14 LD SBDIP 14 LD SBDIP 14 LD Flatpack D14.3 K14.A D14.3 K14.A D14.3 D14.3 K14.A PKG. 14 LD SBDIP 14 LD Flatpack 14 Ld SBDIP 14 LD SBDIP 14 LD Flatpack PKG. DWG. # D14.3 K14.A D14.3 D14.3 K14.A
2
FN6411.1 July 7, 2008
HS-303ARH, HS-303BRH Functional Diagram
TRUTH TABLE
IN N P D
LOGIC 0 1
SW1 AND SW2 OFF ON
SW3 AND SW4 ON OFF
Die Characteristics
DIE DIMENSIONS: 2690m x 5200m (106 milsx205 mils) Thickness: 483m 25.4m (19 mils 1 mil) INTERFACE MATERIALS: Glassivation: Type: PSG (Phosphorous Silicon Glass) Thickness: 8.0kA 1.0kA Top Metallization: Type: AlSiCu Thickness: 16.0kA 2kA Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION: Worst Case Current Density: <2.0 x 105 A/cm2 Transistor Count: 196
Metallization Mask Layout
HS-303ARH, HS-303BRH
IN2 VV+ GND IN1 D4 D2 S4 S2 S1
S3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 3
FN6411.1 July 7, 2008
D3
D1

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